As the demand for higher bit rates in communications systems continues, high-speed signaling schemes are becoming more desirable. Present day standards (e.g. FCC standards) and the physical properties of present day transmission media (e.g. cable attenuation), however, act to limit the available bandwidth in present day systems. As a result, present day systems have adopted bandwidth-efficient line codes to provide broad-band communications.
The term "line code" refers to the waveform pattern of voltage or current used to represent the 1's and 0's of a digital signal on a transmission link. For example, a unipolar line code may be used to transmit the 1's by transmitting a positive voltage and the 0's by transmitting a zero voltage over the communications link. The form of the wave generated by the line code directly affects the bandwidth required to communicate the 1's and 0's over the communications link. As a result, a bandwidth-efficient line code that provides low excess bandwidth is desirable for today's high bit rate communications.
One concern with communications involving such bandwidth-efficient line codes is timing/carrier recovery. That is, the recovery of the clock synchronization at the receiver. A major factor in making such clock recovery at the receiver is the modulation format used to communicate over a bandwidth limited channel. More specifically, it is a concern that modulation formats that provide high bandwidth efficiency through line codes with low excess bandwidth tend to complicate the clock recovery at the receiver, and thus require more advanced signal processing to recover the timing information. An in-depth discussion of this concept can be found in publications such as, Franks, "Carrier and Bit Synchronization in Data Communication - A Tutorial Review," IEEE Transactions on Communications, Vol. 28, No. 8, pp. 1107-1121, August 1980.
Traditionally, timing and carrier recovery is performed through analog circuits. Recently, however, there has been an emphasis on providing digital implementations of such timing and carrier recovery circuits. There are several reasons for the emphasis on the digital implementations. They include: (1) digital circuits eliminate the need for analog circuit tuning; (2) digital circuits eliminate the problems associated with the drift and aging of analog circuits; (3) digital integrated circuits are generally insensitive to process variations, and power supply and temperature variations; (4) digital circuits simplify programmability, and (5) it is relatively easy to convert a digital circuit to different integrated circuit process technologies.
Systems employing bandwidth-efficient codes or signals having low excess bandwidth, however, require extensive filtering to recover the transmitter clock at the receiver. Moreover, when housing a digital clock recovery system in an integrated circuit (IC), additional transistors are required to perform the extra filtering function. As a result, in present-day systems that provide bandwidth-efficient line codes with low excess bandwidth, digital clock recovery systems require a large IC area, and thus increased IC power consumption.
Presently, there are several schemes for clock recovery in such communications systems. One of the simplest signaling schemes for which a clock recovery method has been developed is Non-Return-to-Zero (NRZ) data transmission. Although NRZ transmissions require very simple hardware (i.e. low IC area and low power consumption), they provide high excess bandwidth and low bandwidth efficiency, and thus are undesirable for some of today's high bit rate requirements.
There are, however, several modulation schemes that provide higher bandwidth efficiencies. They include Phase Amplitude Modulation (PAM), Quadrature Amplitude Modulation (QAM), and Quadrature Phase Key Shifting (QPSK). These schemes, however, require complex circuitry, and thus large IC area and high power consumption.
For example, squaring circuits, such as those illustrated in FIG. 1 have been previously used in the art. As shown in FIG. 1, a modulated input signal is input into the squaring circuit, which is then passed through a bandpass filter and a phase locked loop, that generates the clock. Such circuits are well known and are found in such publications as Lee, Digital Communications, Kluwer, 1994. This squaring function has been replaced by other nonlinear functions, such as an absolute value or a power-4 circuit. This method utilizes the cyclostationary property of the incoming signal to derive a clock signal. At sufficiently high signal-to-noise ratio (SNR) and excess bandwidth, the phase locked loop can be replaced by a sign function which translates the output of the bandpass filter to a square wave.
An example of the output of a prior art squaring function is shown in FIGS. 2a and 2b. The power spectrum of a Carrierless Amplitude Modulation (CAP)-16 signal with 100% excess bandwidth is shown in FIG. 2a. The Cap-16 is a 16 point constellation modulation scheme that is very similar to the more well known QAM. The spectrum of the squared signal, shown in FIG. 2b, indicates a clear peak at the symbol rate, 12.96 MHz, which can be further filtered through the bandpass filter and a phase locked loop to get a stable clock with low jitter. The spectral efficiency of this CAP-16 signal is derived as 51.84 Mb/s/25 MHz.apprxeq.2 B/s/Hz.
Another CAP standard, CAP-64, is based on a 155.52 Mbps Physical Media Dependent layer, The CAP-64 standard calls for Carrierless Amplitude Modulation/Phase Modulation with a 64-point constellation and is analogous to CAP-16 above. A system employing CAP-64 may produce an excess bandwidth of 15%. The power spectrum of a system employing the CAP-64 scheme is shown in FIG. 3a. As shown, such a system provides a spectral efficiency of 155.52 Mb/s/30 MHz.apprxeq.5 b/s/Hz.
Squaring the signal gives the spectrum as shown in FIG. 3b. As shown, squaring results in a significant degradation in the peak as compared to FIG. 2b. As those skilled in the art will recognize, this degradation is caused by the reduced excess bandwidth. The energy of this peak, however, is so low that the locking of the phase locked loop becomes unreliable.
An approach to enhance the peak shown in FIG. 3b is to use a different nonlinearity than the square function. Absolute value and power-4 functions have been shown to give a larger peak. However, in a digital implementation, this requires a higher oversampling ratio to avoid aliasing, which severely limits its applicability to broad-band systems.
One proposed solution to derive a more reliable clock for digital standards is the band-edge timing recovery method described in Lee, supra. In the Lee method, only energy in the band edges of the original signal contributes to the peak at the symbol rate. By removing energy from the center of the passband spectrum, the peak-to-noise ratio is increased. This method is shown in FIGS. 4a and 4b. As shown in FIG. 4b, the signal, the spectrum of which is shown in FIG. 4a, is applied to two bandpass filters, BP1 and BP2, with the characteristics shown in FIG. 4a. The output of the bandpass filters are multiplied and further filtered through a third bandpass filter, BP3, which is tuned to the expected symbol rate, and then through a phase locked loop. The spectrum at the output of the multiplier is shown in FIG. 5a and at the output of the third bandpass filter in FIG. 5b. As shown, the peak at symbol rate is significantly enhanced, as compared to that shown in FIG. 3b, and the phase locked loop locks reliably onto to this peak.
A digital prior art implementation of the block diagram shown in FIG. 4b is shown in FIG. 6a. This implementation is similar to that described in Godard, "Passband Timing Recovery in an All-Digital Modem Receiver," IEEE Transactions on Communications, vol. 26, no. 5, pp. 517-523, May 1978. As shown, all digital blocks are clocked with the same clock as the analog to digital (A/D) converter, i.e. N samples are taken during a symbol interval. From the A/D converter, the signal is passed through two parallel bandpass filters, a multiplier, and through a third bandpass filter similar to the circuit shown in FIG. 4b. The decimator and the Sgn block represent a phase detector and a charge pump in a conventional phase-locked loop. This method is well suited for a communication receiver based on a fractionally spaced equalizer with fractional spacing N, for example N=4 or N=3. Each bandpass filter in FIG. 6a can be implemented as a second order IIR filter with two multipliers, as shown in FIG. 6b. The total hardware required for this circuitry, however, includes 7 multipliers and 8 adders all running at the sample rate, which equals N times the symbol rate. This obviously constitutes considerable power consumption and area in an integrated circuit.
One solution for reducing the hardware is to use a single multiplier and adder and, then, clock these at 8 times the sample rate of the A/D converter. Although this would allow time sharing of the hardware, and thus save IC area, it would not save any power consumption. Moreover, this solution is of limited practical use in broadband systems, where the A/D sampling rate might be as high as 50-75 MHz.
Therefore, there still exists a need in the art to provide a low power, and area efficient method and circuit for timing and carrier recovery for broadband, digital communication (in particular modem applications) systems. The present invention addresses this need.